Unified Architecture for Discrete Fourier and Inverse Cosine Transforms
نویسندگان
چکیده
A unified architecture for radix-2 decimation-in-time fast Fourier transform and inverse discrete cosine transform of type II is presented based on constant geometry formulation of the algorithms. The parallelism of the architecture can be specified to meet various throughput and area requirements. The type and size of the transform in the architecture can be configured in run-time. In addition, the maximum size of the transform and word length are parametrizable in logic synthesis.
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